1) Field of the Invention
The present invention relates to a multiple chip package that includes a plurality of integrated circuit (IC) chips enclosed in a single package, and the IC chips in the package.
2) Description of the Related Art
FIG. 1 is a schematic of an internal configuration of a conventional horizontal multiple chip package. As shown in FIG. 1, in the horizontal multiple chip package, a logic chip 1 and a memory chip 2 are laid out horizontally. A clock signal CLK is supplied to the logic chip 1 from outside via an external clock input pad 11. The logic chip 1 outputs an address signal, a control signal, and a data signal, in synchronism with the clock signal CLK. The logic chip 1 also outputs the clock signal CLK via a clock output pad 12. The clock signal CLK is supplied to the memory chip 2 via a wire electrode 31 and a clock input pad 21.
The memory chip 2 inputs the address signal, the control signal, and the data signal, and outputs the data signal, in synchronism with the clock signal CLK supplied from the logic chip 1. A return clock signal CLK (hereinafter, “return clock signal ReCLK”) is supplied from the clock input pad 21 of the memory chip 2 to the logic chip 1, via a wire electrode 32 and a return clock receiving pad 13 of the logic chip 1. The logic chip 1 receives the data signal from the memory chip 2 in synchronism with the return clock signal ReCLK.
FIG. 2 is a schematic of an internal configuration of a conventional stacked multiple chip package. As shown in FIG. 2, in the stacked multiple chip package, the logic chip 1 and the memory chip 2 are vertically stacked. Similarly to the horizontal multiple chip package, the clock signal CLK output from the clock output pad 12 is returned to the return clock receiving pad 13 of the logic chip 1 as the return clock signal ReCLK, via the clock input pad 21.
In both of the horizontal multiple chip package shown in FIG. 1 and the stacked multiple chip package shown in FIG. 2, the clock output pad 12, output pads 14 of address signals and control signals, the return clock receiving pad 13, and input/output pads 15 of data signals are all disposed along one side of the logic chip 1. The clock input pad 21, input pads 22 of address signals and control signals, and input/output pads 23 of data signals are all disposed along one side of the memory chip 2. Clock trees 16 and 17 and a latch circuit 18 inside the logic chip 1, and a clock tree 24 and a latch circuit 25 inside the memory chip 2, respectively adjust the input timing and the output timing of the control signal, the address signal, and the data signal so that these timings become uniform.
In recent trend, the number of pins in the multiple chip package is increasing. This requires wider band width and higher clock frequency. Therefore, the adjustment of timing inside the logic chip 1, the adjustment of timing inside the memory chip 2, and the adjustment of timing between the chips become more difficult. FIG. 3 is a schematic of an internal configuration of a conventional stacked multiple chip package having multiple pins.
As shown in FIG. 3, in the multiple-pinned logic chip 1, the input/output pads 15 of data signals are disposed not only along a side (a right side in FIG. 3) on which the clock output pads 12 and the return clock receiving pads 13 are disposed but also along another side (a left side in FIG. 3). The clock signal CLK is supplied to the data output side of the latch circuit 18 connected to the input/output pads 15 at the left side, via the clock tree 16 of the clock signal CLK. The return clock signal ReCLK is supplied to the data input side of the latch circuit 18 connected to the input/output pad 15, via the clock tree 17 of the return clock signal ReCLK.
In the multiple-pinned memory chip 2, the input/output pads 23 of data signals are disposed not only along a side (the right side in FIG. 3) on which the clock input pads 21 are disposed but also along another side (the left side in FIG. 3). While the intermediate part of the clock tree 24 of the clock signal CLK is not shown in FIG. 3, the clock tree 24 is actually extended to the left side from the clock input pad 21 at the right side. The clock signal CLK is supplied to the latch circuit 25 connected to the input/output pads 23 at the left side, via the long clock tree 24.
There is a memory control circuit configured as follows. In the memory control circuit, a data bus driver and a receiver are disposed in isolation. The data bus is connected from the driver of the data bus to the receiver. A memory module of a synchronous dynamic random access memory (SDRAM) is connected to the data bus. A clock signal line is connected to each SDRAM such that signal propagation delay times are equal, and a signal works as a synchronization signal for fetching data read by the receiver of the memory control circuit. Such a memory control circuit is disclosed in, for example, Japanese Patent Application Laid-open No. 2000-194594. According to a technology disclosed in this patent literature, a difference between the phase of the read data and the phase of the reading clock can be kept constant. Even when number of mounted SDRAM dual in line memory (DIMM) increases, timing margin between the read data and the reading clock can be maintained.
A semiconductor memory that includes internal circuits that operate following clock signals, and a plurality of independent clock input terminals that supplies the clock signals to the internal circuits of the semiconductor chips is disclosed in, for example, Japanese Patent Application Laid-open No. H3-198283. According to the technology disclosed in this patent literature, the length of a clock signal line within the semiconductor chips can be shortened. Therefore, impedance of the clock signal line becomes small, and a deviation of the clock signals due to positions on the semiconductor chips can be made smaller.
According to the above multiple chip package that includes the multiple pins, a delay of the clock signal CLK between the logic chip 1 and the memory chip 2 is small. However, the input/output timings of all the signals of the logic chip 1 are adjusted based on one clock signal CLK and one return clock signal ReCLK. The input/output timings of all the signals of the memory chip 2 are adjusted based on one clock signal CLK. Therefore, the wiring lengths of the clock trees 16, 17, and 24 within the chips 1 and 2 become long, and delays of the clock signal CLK and the return clock signal ReCLK within the chips 1 and 2 become large. On the other hand, when the clock frequency becomes high according to the increase in the number of pins, a timing window becomes small. Therefore, it becomes difficult to adjust timings.